The present invention relates to a semiconductor device.
It is known that a waveform of pulses that are transmitted sequentially via logic circuits including P-channel MOS transistors is deteriorated by NBTI (Negative Bias Temperature Instability).
NBTI means that a threshold voltage of a PMOS transistor varies by continuous application of a negative gate bias to the PMOS transistor.
For example, in Patent Document 1 (Japanese Published Unexamined Patent Application No. 2006-33058), an embodiment is described in which a two-input NAND circuit is applied for clock gating. This embodiment sets forth that one input of the two-input NAND circuit is fixed to H and that a PMOS influenced by NBTI in the NAND circuit is divided into two parts to distribute the NBTI influence.
A semiconductor device described in Patent Document 2 (Japanese Published Unexamined Patent Application No. 2006-74746) includes a first semiconductor integrated circuit that has a predefined function and outputs a required output signal and a second semiconductor integrated circuit having a plurality of MOS elements that switch between conducting and non-conducting states independently of each other, in response to a plurality of gate signals with shifted timing, the MOS elements being coupled in parallel to the output or input of the first semiconductor integrated circuit. This semiconductor device further includes a pulse generating circuit that generates and outputs the gate signals with shifted timing to the MOS elements in the second semiconductor integrated circuit.